A computing system generally includes a processor coupled to internal memory, including flash or Random Access Memory (RAM), and external memory devices and peripheral devices. A bus generally provides an interface between the processor and the external memory, the on-chip memory, and other peripheral devices. A bridge may be used to couple a high-performance bus with a memory bus, enabling high-bandwidth devices such as the processor to communicate with internal memory, external memory, or other peripheral devices in the system. The bus on both sides of the bridge may use various protocols to govern the transfer of instructions and responses. The bridge generally converts the protocols utilized by the processor (the front end) to the protocols utilized by the memory devices and peripheral devices (the back end).
Bus transfers may include read or write operations for data objects, which may take one or more clock cycles. Some processor architectures are sequential, which requires each instruction to complete, including the return or writing of any data, before the next instruction can be issued and executed. An example of a sequential bus is the Advanced High-Performance Bus (AHB). Under the AHB protocol, a master device may be granted access to the bus. Only one master can access the bus at any given time. The master can send a read or write request over the bus to attached slave devices. Each instruction and response should be completed before another instruction is initiated or before another master can access the bus. The AMBA Specification (document number IHI 0011A), which is incorporated in its entirety by reference herein, fully describes the AHB protocol and can be found at the ARM website, www.arm.com.
Modern bus connections between the elements of the system are no longer limited to sequential processing, but can now process commands in parallel. Therefore, multiple read and write requests may be sent to the various memory elements at the same time. An example of a parallel bus is the ARM Advanced eXtensible Interface (AXI), which takes advantage of separate channels for read and write transactions, and supports parallel processing of various read and write requests. The AMBA AXI Protocol Specification (document number IHI 0022B) can be found at the ARM website, www.arm.com, and is incorporated in its entirety herein by reference. When taking advantage of a parallel bus, maintaining data coherency may become difficult. As each instruction and response time may take varying clock cycles to complete, and each instruction may be carried out independently, the instructions may complete out of sequence if a controller is not responsible for resequencing the commands and returned data.